Process Integration Engineer

Company Name:
Career Development Partners
A Process Integration / Technology Development Engineer defines, develops and implements silicon process technology for the manufacture of integrated silicon devices. The successful candidate will be responsible for design rule definition, device architecture, process flow implementation, process module development, electrical characterization, and technology qualification for new silicon technology developments and transfers of existing silicon technologies in and out of the resident fab.
Primary Tasks, Duties, and Responsibilities:
o Define device architecture, technology design rules and electrical target specifications.
o Create technology process flows with process specifications.
o Process module development and characterization
o Define test structures for process integration and process module development.
o Design statistical experiments and analyze results to optimize device architecture and/or process modules.
o Coordinate process unit and process module development.
o Drive process and device optimization.
o Facilitate process improvements and/or fixes for problems of poor reliability or low yield.
o Support Process Engineering and Yield Engineering groups to improve process quality and yield of technologies released to manufacturing.

Position Requirements
o MS/PhD in Electrical Engineering, Physics, Chemistry, Chemical Engineering, Materials Engineering or related technical field, PhD preferred.
Required and desirable skills:
o Solid understanding of semiconductor device physics including CMOS, DMOS and Bipolar devices.
o Good knowledge of discrete devices including low, medium and high voltage platforms.
o Background in semiconductor process technology and wafer fabrication
o Experience with 180 nm required. Experience with 130, 90 or 65 nm desired.
o Experience with design and evaluation of physical and electrical design rule test structures
o Knowledge of one or more of the following technologies: Silicon on Insulator (SOI), CMOS Image Sensors (CIS), EEPROM, Dual Damascene copper integration
o Knowledge of one or more of the following engineering disciplines: Process Integration, Design, Modeling, and/or Process Engineering.
o Knowledge of one or more Wafer Level Reliability (WLR) and Intrinsic Reliability testing methodology, such as gate oxide integrity (GOI), VRamp, time dependent dielectric breakdown (TDDB), hot carrier injection (HCI), electromigration (EM), stress migration (SM).
o Knowledge of device and process simulations, TCAD desired.
o Foreign language skills is desirable but not required (Japanese is the most desirable; Dutch, French, Russian or Czech are also useful).
o A US citizen or permanent resident is desirable.
o Ability to characterize process modules and device performance with test analyzer equipment
o Ability to utilize DOE and statistical analysis is required.
o Excellent written and oral communication skills.
o Must be an effective team player
o Proven problem solving ability.

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